Biography: I am presently a Postdoctoral Fellow under the supervision of Prof. Suman Datta at School of Electrical and Computer Engineering, Georgia Institute of Technology (GaTech). My current research is mainly on back-end-of-line (BEOL) compatible oxide transistors for enabling advanced computing (e.g., in-memory computing) hardware and monolithically 3D integrated functional backside (e.g., power delivery network) at leading-edge logic nodes. I received my Ph.D. degree in Electronic and Computer Engineering from the Hong Kong University of Science and Technology (HKUST) under the supervision of Prof. Hoi-Sing Kwok in 2020. Afterwards, I have served as a postdoctoral research associate for 1.5 years, continuing my Ph.D. research on metal oxide thin-film electronics at State Key Laboratory of Advanced Displays and Optoelectronics Technologies (SKL of ADT), HKUST. Also, I worked with Prof. Ching Wan Tang and Prof. Shou-Cheng Dong to develop advanced silicon nitride shadow masks (SiNMs) for direct patterning of ultra-high-resolution RGB side-by-side OLED micro-displays. From Sept. 2021 to Aug. 2022, I was a postdoctoral researcher in cooperation with Prof. Shriram Ramanathan at Purdue University, West Lafayette., where I focused on strongly correlated oxide electronic/ionic devices and circuits for neuromorphic computing hardware. Before my Ph.D. study, I obtained my B.S. degree in Optical Information Science and Technology from Huazhong University of Science and Technology (HUST), Wuhan (advisor: Prof. Jun Zhou). I have co-authored >40 peer-reviewed papers, >30 conference proceeding articles, 1 book chapter, and 6 US/China patents. I was a recipient of Distinguished Paper Award at International Display Manufacturing Conference (IDMC) in 2015 and 2017, Best Presentation Award in Postgraduate Workshop on Display Research in 2016 and 2018. I also received the Distinguished Paper Award and was interviewed by the Young Engineers Spotlight (YES) at SID Display Week 2021. I was selected as an invited speaker of the 2021 Young Leader Conference at International Conference on Display Technology (ICDT), and is now a member of display future star committee of SID China.
Office: 4140 Marcus Nanotechnology Building, 345 Ferst Dr NW, Atlanta, GA 30332, USA Email: sdeng76@gatech.edu Tel: 1 (765) 746-9154
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Metal oxide semiconductors are expected to be one of the most promising TFT channel materials. However, with the development of information displays and Internet of Things (IoT) technology, technical standards of MO TFTs become increasingly higher. The prevalent amorphous indium-gallium-zinc oxide (a-IGZO) devices always suffer from technical issues such as mobility inadequacy and device instability. Our efforts are being made on the continuing improvement of electrical characteristics and reliability of MO TFTs. Taking advantage of a collaborative modification on element composition and crystal morphology, we have developed hybrid-phase metal oxide (hp-MO) thin films, the electron Hall mobility of which (>30 cm2/Vs) could surpass the amorphous counterpart's theoretical upper limit, as more competitive MO TFT channels but without increasing material costs. Through processing innovations (e.g., gate insulator engineering, gate electrode engineering, and planarization-enable fluorination), a series of hp-MO TFTs including etch-stopper, self-aligned, and vertical devices can be fabricated with high electrical performance and robust device stability. These devices can further serve as cost-effective energy-efficient building blocks, participating in the demonstration of a wide range of electrical applications such as transparent electronics, micro-displays, augmented reality, and sensor interfaces.
Device interconnect separation to frontside signal lines and backside power delivery can bring about improvements of IR drop and CMOS area scaling. As the industry is transitioning into the backside power delivery solutions for leading edge node, there is a demand to develop strategies to extend such vertical power delivery networks across multiple tiers of the M3D stacked circuits and systems. The 48 V to 12 V conversion might occur on the package or interposer level, while the 12 V to 3 V or 1 V conversion might occur within the M3D stack to allow maximum efficiency. It is also recognized the different voltage domains may exist in a M3D stack, for instance, 0.8 V for FEOL silicon logic circuitry, 1.6 V for supporting embedded DRAM on the MEOL tier, and 3.2 V for programming non-volatile memories (e.g., FeFET or RRAM) on the BEOL tier. Hence, voltage converters and regulators are needed across the M3D stack. One challenge to integrate power transistors at the BEOL is the thermal budget (<400 ℃), which prevents the compelling technologies such as GaN to be deployed in the 3D sequential integration schemes. To overcome the challenge, we have developed a tungsten-doped indium oxide (IWO) power transistor technology, which is compatible with the BEOL integration. Moreover, considering a lack of high-performance p-type oxide semiconductors and undesired threshold voltage drop in enhancement-mode devices, we have further developed a monolithic co-integration technology, where both enhancement- and depletion-mode power transistors could be integrated on the same chip to enable efficient voltage conversion of on-chip switched-capacitor DC-DC converters. In addition to power delivery, we are also making efforts to migrate more system functions (e.g., global signal routing) to the CMOS backside.
In the search for the next generation AI hardware, explorations into technologies beyond CMOS have led to the development of materials and novel device structures that are tailored specifically for neuromorphic circuits and applications—breaking the memory bottleneck. Various physical phenomena have been exploited, such as ion migration, electron migration, phase change, ferroelectricity, magnetic tunneling, insulator-to-metal transitions (IMTs). The key idea behind all of these is to utilize intrinsic physics to enable efficient computation with substantial performance-power-area-cost (PPAC) advantages by replicating the functionalities of biological neurons and synapses. Strongly correlated oxide materials are particularly suited for these studies owing to their vastly tunable physical properties over multiple timescales by subtle external stimulus, and can emulate various neuronal and synaptic functionalities found in biological brains. However, different neural functions usually relies on different material systems. We hypothesize that the ability to perform multiple neural functions with the same material system can simplify the chip-scale fabrication process among other benefits. Especially when new materials that have never been introduced in a fab are being considered, if they can offer more than one compelling device application within the same technology domain, then the chances of their consideration naturally become greater. Therefore, we borrowed the concept of selective doping from integrated circuit industry and applied selective hydrogen doping to quantum materials (e.g., VO2). By locally configuring pairs of catalytic and inert electrodes that enable nanoscale control over carrier density, volatility or nonvolatility could be appropriately assigned to each two-terminal Mott memory device per lithographic design, and both neuron- and synapse-like devices were successfully integrated on a single chip. Our recent work further demonstrated partially hydrogenated VO2 as potential p-bit generators based on the stochastic IMT relaxation dynamics. The phase transition threshold characteristics and p-bit values of the post-fabricated devices were controllable by gentle forming gas annealing, offering an interesting direction to further explore hardware for probabilistic computing.
An ideal display for virtual/augmented reality (VR/AR) with a truly immersive experience should at least have a 2-inch screen for accommodating a field of view (FoV) of 105°, and a pixel density of 2000 ppi for eliminating screen door effect. However, RGB side-by-side OLED displays that are currently used in most VR/AR headsets have pixel densities between 600 and 800 ppi due to the technical limitations of conventional fine metal masks (FMMs). On the other hand, white OLED micro-displays with a color conversion scheme are feasible to realize pixel densities exceeding 2000 ppi, but their panel size is typically limited to <1 inch by the CMOS backplanes, and the optical efficiency is greatly reduced by the color filter array. To address these issues, we have developed a process to produce a robust silicon nitride shadow mask (SiNM) for directly patterning ultra-high-resolution, RGB side-by-side OLED displays. So far, the ultra-flat self-tensioned SNMs with a max. diagonal size of 3 inch and a max. pixel density of 5000 ppi on 4-inch silicon wafers have been fabricated in high yield.
To be updated...